This relates to semiconductor devices such as FinFETs (Fin Field Effect Transistors).
A conventional field effect transistor (FET) is an essentially planar device having a gate structure that extends across the surface of a semiconductor such as monocrystalline silicon and doped source and drain regions in the semiconductor on either side of the gate. The gate is insulated from the semiconductor by a thin layer of an insulator such as silicon oxide. A voltage applied to the gate controls current flow in an un-doped channel that extends between the doped source and drain regions in the semiconductor beneath the gate.
The switching speed of the FET depends on the amount of current flow between the source and drain regions. Current flow depends on the width of the gate where width is the direction in the channel that is perpendicular to the direction of current flow. With the continuing demand for higher speed transistors for use in communication and computer equipment, there is a continuing interest in making transistor devices with wider gates.
FinFETs have been developed to obtain larger gate widths A fin is a thin segment of semiconductor material standing on edge, thereby making available multiple surfaces for the formation of gate structures. FIG. 1 depicts an illustrative FinFET 100 comprising four fins 110, 120, 130, 140 and a common gate structure 150. The fins have first and second major surfaces, such as surfaces 112, 114, that are opposite one another and usually are symmetric about a center plane that bisects the fin lengthwise. Major surfaces 112, 114 are often illustrated as being parallel as in U.S. Pat. No. 7,612,405 B2 or Pub. No. US2008/0128797 A1, which are incorporated herein by reference; but process limitations usually result in surfaces that slope outwardly from top to bottom of the fin with the result that the cross-section of the fin is trapezoidal in shape. In some cases, sidewalls 112, 114 meet at the top. FinFET 100 has a common gate structure. In other embodiments, a separate gate structure may be located on each surface of each fin. The width of the gate structure 150 shown in FIG. 1 can be as much as N(T+2H) where N is the number of fins, T is the distance, if any, between the first and second major surfaces of the fin and H is the height of the fin.
Doped source and drain regions are located on opposite sides of the gates. As in a planar FET, a voltage applied to the gate controls current flow in an un-doped channel that extends between the doped source and drain regions in the semiconductor beneath the gate.
While FinFETs make possible the formation of transistor structures of considerable width, the process of forming FinFETs limits the number of different gate widths that can readily be formed. Since fins are typically formed by etching parallel channels into a semiconductor material from a flat surface and since the etching rate is the same for each channel, the height of each fin that is formed is approximately the same. As a result, readily achievable gate widths are available only in discrete steps. For optimal device sizing, however, there is a need for finer granularity in available gate widths. Efforts to provide such variations in widths as described in the above-referenced U.S. Pat. No. 7,612,405 B2 or Pub. No. US2008/0128797 A1 are complicated and introduce too many additional steps into the fabrication process.